© 2008 Brad Brannon, Analog Devices, Inc.
Abstract
Analog-to-digital converters (ADCs) perform a vital function in a wide range of consumer and industrial applications, translating continuous time signals into digital data that FPGAs, DSPs and ASICs can then process. While most engineers understand SNR and harmonic distortion, many vital specifications are often misunderstood or even overlooked, usually to the detriment of the end design.
Introduction
Over the last decade, advancement in semiconductor technology have led to a flood of ADCs in the market. It is sometimes difficult to know which ADC is best for a given socket. Often times data sheets only confuse the issue. To compound this confusion, many specification impact performance in unanticipated ways. All too often when selecting converters, the user simply looks at bits or SNR or harmonic distortion. While these specifications are important, others can be equally important. For more details on the specifications discussed below and many other common ADC specifications, see Analog Devices applications note AN-835 [1].
Specifications
Resolution
Perhaps the most
misunderstood specification in a data converter is resolution. This refers to
the number of output bits of the device, but fails to provide any indication of
the device’s performance. While most engineers are familiar with the equation
,
which predicts SNR in dB (‘N’ is the resolution of the converter), they are less
familiar with the fact that other issues limit SNR, including thermal noise,
clock jitter, DNL errors and other anomalies. This is especially true for high
performance, high resolution converters.
Some data sheets
provide the Effective Number of Bits (ENOB), which solves the equation above for
‘N’ using actual SNR measurements to compute a number of bits that represents
the converter’s actual performance. While this is better, a more useful gauge of
converter performance is noise spectral density, specified in either dBm/Hz or
.
While dBm/Hz requires that the input impedance be known, the latter does not.
Either of these may be calculated by knowing the sample rate, input range, SNR
(from the datasheet) and input impedance (for dBm/Hz). Once either of these is
known, a converter can be selected that matches the analog performance of the
circuit prior to the converter. This is a much better method of selecting an ADC
than by simply stating the resolution.
Many users are also concerned with spurious and harmonic performance of the converter. It is not well understood by many users, but harmonics and spurious performance are completely separated from the resolution of the converter. It is possible to have a 2-bit ADC that has perfect harmonic performance. What is also not commonly known is that IC designers adjust their designs such that harmonics fall into line with expectations for the resolution of the converter they are designing. Designers have wide latitude to adjust parameters such as power, sample capacitor size, and circuit complexity to achieve their target harmonic performance. Within these bounds, they have much freedom to achieve the desired performance goals. Therefore, when selecting a converter, closer attention should be paid to its SNR and SFDR than to its bit resolution.
PSR
Power Supply Rejection is a measure of the amount of signal on the power supply that is coupled to the sample network of the ADC and appears in its digital outputs. Many converters only have 30 to 50 dB of PSR. Therefore, noise and signals that are present on the rated power supply line will appear in the output only 30 dB to 50 dB below their input level. Normally, the unwanted signal on the power supply pin(s) is relative to the input range of the converter. Therefore, if the noise on the power supply pin is 20 mV rms and the input range of the converter is 0.7 V rms, then the noise level on the input is –31 dBFS. If the converter has a 30 dB PSR rating, then the noise (assuming a coherent signal) would show up as a –61 dBFS spectral line in the output. PSR is an important part of determining how much filtering and decoupling the power supply pins of the converter will need. PSR is an important rating in any environment with the potential for high noise on the power supply. Examples include applications with switching supplies (as opposed to linear supplies), applications with large common-mode signals on the power supplies and grounds (such as a transmitter), and applications that operate in large magnetic or electrostatic environments (medical and industrial imaging). Failure to properly select and apply PSR to an application will result in reduced noise and spectral performance.
Figure 1
CMR
Common Mode Rejection is the ratio of the induced differential mode signal in the presences of a common-mode signal. Many contemporary ADCs employ differential inputs in order to provide a large immunity to common-mode signals present in the system and to take advantage of the fact that differential input structures naturally reject even order distortion products. As with PSR, common-mode signals can be induced by power supply ripple, high power signals induced on the ground plane, RF leakage through mixers and RF filters and applications where high electric and magnetic fields are found. Many converters do not specify CMR, and care must be taken in reviewing this specification when important. Many converters have excellent performance of between 50 dB and 80 dB. Figure 2a shows the response to a common-mode signal on a single-ended input of an ADC. In this case, the common-mode signal becomes part of the analog input and is digitized accordingly. In figure 2b, the same input is configured as a differential-mode input and the common-mode signal is almost completely rejected by the converter.
2a Single Ended Input with noise 2b Common Mode Response
Clock Related Specifications
There are a number of clock related specification that have wide ranging significance. Unfortunately, these are not always specified and can be difficult to determine. Nonetheless, they are often important for a wide range of reasons as indicated below.
Figure 3. The relationship between the input clock and sample noise.
Input Slew Rate
Clock input slew rate is the minimum needed slew rate to achieve the rated performance. Most contemporary converters have sufficient gain on the input clock buffer to ensure that the sample instant is well defined. However, if the input slew rate is sufficiently slow so as to produce a high degree of uncertainly of the sample moment, excess noise will result as noted in [2] and [3]. If a minimum input slew rate is specified, the users should meet that requirement to ensure the rated noise performance.
Aperture Jitter
Aperture jitter is the internal clock uncertainly to the ADC. As noted in [2] and [3], the noise performance of the ADC is limited by the jitter of the clock, both internal and external and is defined as:
The aperture jitter specified in a typical data sheet is for the converter only. The external aperture jitter must also be taken into account and sums in an rms manner with the internal aperture jitter. For low-frequency applications, jitter may be unimportant, but as the analog frequency increases, noise due to jitter becomes an increasing concern, as shown in the equation. Failure to use an adequate clock will result in poorer than expected performance.
In addition to increased noise from clock jitter, an additional phenomenon occurs during the sample process. As noted in [3], the ADC sample process is partly composed of convolution in the frequency domain. As such, any spectral lines in the clock signal that are not harmonics of the clock signal itself will be convolved onto the digitized output, showing up as output distortion. Therefore, the clock signal supplied to the ADC should have the highest spectral purity possible and posses a jitter as defined by the application and the equation above. One of the largest mistakes made with contemporary converter applications is to use an FPGA to generate the clock source for the data converter. FPGA output drivers are among the worst choice in terms of jitter. Clock distribution should be left to low noise clock drivers such as the AD9516 to ensure optimal converter performance. [2]
Aperture Delay
Aperture delay is the time delay between the application of the sample signal to the converter and the moment the input signal is actually sampled. In most contemporary converters this time is very small, being on the order of a nanosecond or less, and may be positive, negative or even zero. For many applications, aperture delay is unimportant. However, if exact sample instant is important to know, then aperture delay will be important.
Conversion Time and Conversion Latency
Conversion time and latency are two very closely related specifications. Conversion time generally applies to converters such as successive approximation converters (SAR), where a high-frequency clock is used to process the input signal that appears on the output at a time much later than the conversion command but prior to the next conversion command. The time between the conversion command and the completion of the conversion (a signal pin is usually provided to indicated that conversion is complete) is the conversion time. Conversion latency, a measure of the number of pipelines or internal digital stages that are used to produce the digital output, is usually important with pipelined converters. Latency is usually stated in terms of pipeline delays. Actual conversion time may be calculated by multiplying this number by the sample period used in the application.
Both of these specifications are important in applications in which time must be accurately known, such as in feedback systems where loop constants must be accounted for to ensure a stable response, or in applications such as telecommunications where excess latency in the processing stages can create networking issues. In many cases, converter latency alone may not be an issue. However when combined with other signal processing, it may become a significant issue for select applications.
Wake-up Time
In power conscious applications, the device is commonly powered down during periods of inactivity to conserve power. While this does save considerable power, a finite amount of time is required for internal references to stabilize and for the internal clock functionality to resume when the device is turned back on. During this period of time, conversion data produced by the device will not meet specifications, or, in the worst case, the data may be corrupt. To ensure accurate data, the application should wait the specified amount of time before using the data produced. This will require the converter to be turned on sufficiently early to guarantee accurate data at the point in time that it is needed.
Output Loading
Like any digital output device, ADC specifications include an output drive capability, especially CMOS output devices. While important to know for reliability reasons, the output load should be minimized in order to maintain maximum performance. A quick look at a typical data sheet may indicate that to the device can drive a 50-mA load. Internally this current must pass through the die, wire bonds and pin. Each of these elements includes resistance and inductance. Therefore, a voltage is induced across these elements that can couple into the analog input of the device. In a practical circuit, a 10-pF capacitive load driven by a CMOS driver slewing at 1-V/ns will draw 10 mA of current during the slew. If 16 bits are switching, the total current could be as high as 160 mA. A 0.1-ohm resistance would cause a 16-mV voltage drop. On a 16-bit converter with a 2-V range, this is over 500 LSBs of potential noise that could couple back to the input. Therefore, in all high-performance applications, not only is it important to minimize the output loading, but it is equally important to ensure that the device is properly decoupled and that the layout is optimized to ensure a minimum voltage drop on the supply pins. Failure to follow these guidelines can significantly reduce the performance of the converter. To avoid some of these problems, many converters provide LVDS outputs. Because LVDS is a differential output device, switching currents are reduced and overall performance can be improved. If available, LVDS outputs should be used to maximize performance.
Unspecified Criterion
One unspecified item that is of vital important is layout. Very little can be specified about this, yet it can impact converter performance in a very significant way. Interestingly, many of the specification above are directly impacted by poor layout practices. A poor layout always results in degraded performance.
For example, if the application failed to include sufficient decoupling capacitors, excess power supply noise would exist. Because of finite PSR, noise on the supplies would couple into the analog inputs, corrupting the digital output spectrum of the ADC as shown in figure 4b.
Figure 4a. Performance with caps Figure 4b. Performance with limited caps
Other specifications, such as CMR, have similar sensitivities. Less obvious may be the fact that noise coupling to the encode clock may modulate the clock and result in this noise being convolved with the analog input, resulting in additional spurs on the output spectrum.
Conclusion
While many engineers focus on dynamic specifications such as SNR and SFDR, they often fail to consider the implication of other less common specifications. Many on these have performance implications. More interesting is how these secondary specifications may in fact limit the performance of the more common specifications. Thus, when selecting a converter for an application, it is always wise to consider all of the specifications, even those that may seem unimportant, as these may actually be the ones that limit performance in the end. Because selecting a converter can be confusing, using a behavioral model to simulate the application can help reduce selection time as well as ensure selection of the best converter for the application from the start. Behavioral models are available to aid in this and are suitable for use in Matlab, C++, LabVIEW, VisualAnalog™ and ADS environments [4].
References
1. Analog Devices Applications note AN-835, “Understanding High Speed ADC Testing and Evaluation”, Brannon and Reeder, www.analog.com.
2. Analog Devices Applications note AN-501, “Aperture Uncertainty and ADC System Performance”, Brannon and Barlow, www.analog.com.
3. Analog Devices Applications note AN-756, “Sampled Systems and the Effect of Clock Phase Noise and Jitter”, Brannon, www.analog.com.
4. ADIsimADC™, www.analog.com/adisimadc.