Introduction

The introduction of fast, inexpensive digital signal processors (DSP) technology, has allowed them to find applications into areas that were once dominated by analog circuitry.  Today, DSP’s are often used in place of mixers, oscillators, filters and detectors of analog signals of all types as well as in areas not possible to implement in the analog domain.  This of course has caused a collateral increase in the demand and usage of analog to digital converters (ADC) as well.  Once an analog signal has been digitized, all varieties of manipulation may be performed in the digital domain.  Interestingly enough, in the digital domain the math can be made as linear (or non-linear) as desired!  The same cannot be said for ADC technology.  Although the last few years have seen significant improvements in ADC linearity, they are still one of the bottlenecks in terms linearity limitations.

 

The purpose of this article is to help the reader understand the various type of distortion found within an ADC and to examine various techniques for determining the performance limitations they cause.

 

Introduction to Types of Distortion

Distortion within data converters comes from several sources.  They can be categorized into two main groups.  The first is static and consists of ‘dc’ errors in the transfer function.  The second are those with dynamic nature.  Dynamic errors are associated with poor frequency response. 

Static

DNL

Differential non-linearities are deviations of any code width from an ideal 1 LSB.  As such, DNL errors are usually thought of as part of the quantization error.  DNL errors do have an important impact on the linearity of an ADC.  Most high-resolution converters are built with one of several multi-stage architectures such as sub-ranging, pipelining or other appropriate technique.  As such, DNL errors at the overlap points tend to be cumulatively either long or short creating a localized linearity error as shown in the exaggerated plot below.  Although a data converter may be specified to within +/- ½ lsb, if 6 errors occur closely spaced, these DNL errors will combine to cause a cumulative linearity error of 3 lsbs.

 

 

While DNL errors are localized and may have little or no effect on large signal performance, they can become quite significant at very low signal levels.  This is especially true if the errors are at midscale as is often the case.  In cases where the input is AC coupled, small signals will center on the ADC midscale.  If the converter has a localized linearity error at midscale, severe distortion will occur as can be seen in the midscale zoom of the transfer function above.  While it is difficult to predict what the exact nature of the distortion will be, it should be clear that serious distortion would result. 

 

INL

Beyond the localized linearity error mentioned along with DNL, global linearity errors also exist.  This is caused by the Integral non-linearity or INL.  INL is the deviation of the transfer function from a reference line measuring in fractions of 1 lsb using a ‘best straight line’ determined by a least square curve fit or end fit method. 

 

Normal INL errors are more straight forward than DNL errors and in many cases may be modeled using fairly low order Taylor series expansions in the form:

 

 

Dynamic

There are many types of dynamic linearity errors within data converters.  Dynamic errors are those that have the characteristic of being frequency dependent. 

 

Slew Rate

The most common form of dynamic linearity error is slew rate limitation.  Inadequate bias currents in one of the many analog stages are generally the leading cause of this type of distortion. 

 

Other forms of dynamic linearity include those that relate to device physics.  One such example is non-linear junction capacitance within the design.  The capacitance of a PN junction is dependant on many things.  Not only doping profiles and device geometry, but also operating voltage.  As the analog input signals change within a linear stage, the junction capacitances of the responding devices also change.  This non-linear capacitance causes the linearity to change not only with respect to the instantaneous voltage, but also with regard to the slew rate since the current flowing through this capacitance changes with the derivative of the analog voltage presented across the junction.  As these currents dynamically change, the resulting IR (or IZ) drops within the device cause errors in current to be translated to voltage.

 

Symptoms of dynamic distortion are worsened spurious performance as the analog frequency increases.  In general terms, the same type of Taylor series expansion can be used to describe dynamic performance.  The differences being that the coefficients have strong frequency dependency and the terms are complex (in the form of a + j b) and not just simple scalar as will be shown later.

 

Aperture Errors

Of all the converter dynamic errors, aperture error is one of the least understood and most difficult to explain.  In most cases, the sampling process is assumed to be instantaneous with a unit impulse that is infinitely narrow.  However, in reality, the sampling process takes place over a finite time.  Like a shutter on a camera, if the subject moves while the shutter is open, the image will be blurred.  Likewise if the analog input signal changes while the signal is being sampled, the signal will be distorted. 

 

 

As shown in the figure above, in the ideal case with a unit impulse, the analog signal is accurately sampled.  However, in the second case, the unit impulse has been replaced with a triangular sampling signal.  In this case, the signal is sampled by integrating the analog input with the triangular function described by the pulse.  This has a number of effects.  The first is that it has the characteristic of low pass filtering the sampled signal, limiting the bandwidth of the sampling process.  The second effect is that the non-linear edges of the sample signal will integrate a non-linear portion of signal into the sampled sum causing addition non-linearity.  The effect is magnified as the analog input frequency increases. 

 

Fortunately, this type of distortion is minimized by fast logic and good design practices.  However, as ADCs continue to increase in their analog bandwidth, this phenomenon may become a more significant portion of the distortion.

 

Composite

Unit Circle Effects

When examining the distortion, two components can be identified.  The distortion can be considered as a vector with a magnitude and phase component.  As the frequency increases, the magnitude of the distortion typically increases as previously discussed because of the frequency dependant nature.  In addition, the phase angle of this distortion will rotate due to the linear phase characteristics of the analog chain of the converter.  This is shown in the figure below as an increasing magnitude as frequency increases as well as an increase in phase shift.

 

 

As discussed earlier, the static linearity of data converters changes relatively little as the frequency increases.  As such, the magnitude and phase angle of the DC transfer function for a given distortion product stays relatively constant as shown in the next figure. 

 

 

Since the distortion is now defined in terms of vectors, the static and dynamic performance of a data converter can be summed together.  In fact, it is possible for the terms to exactly cancel out as shown below causing such a converter to have better mid-band performance than at either lower of higher frequency.  This phenomenon is frequently observed as fluctuations in the SFDR of a converter as the input frequency is swept through the input bandwidth.

 

 

As shown in this figure, both the static and dynamic distortion are shown.  In addition, the net distortion is shown in dashed red.  This is the vector summation between the static and dynamic.  Notice that at frequencies 1, 2 and 4, the magnitude is not significantly different, only the phase rotated.  However at frequency 3, the phase between static and dynamic are 180 degrees out of phase and the resultant vector is 0.  Not only can harmonics cancel, they can also be magnified if the phases align, rather than cancel, resulting in very large harmonics. 

 

 

Considerations

Fortunately, most wideband converters do not exhibit this problem.  However, care must be taken when selecting or characterizing a converter to pay close attention to these issues.  Evaluating a converter at a single frequency, even in the center of the band of interest could be problematic.  As shown in the harmonic plot above, the second harmonic has a local minimal within a few megahertz of a local maximum.  If you were to characterize the device at one or the other, performance would be significantly different at the other (better or worst).  Therein lies the importance of carefully selecting the converter for your application, wireless or otherwise.  Similarly, if your harmonic distortion is this turbulently effected, it is also likely that the converter has linear phase (group delay) issues.

 

Commonly Specified

Harmonics (aka SFDR)

Often harmonics and SFDR are misused and often confused.  Harmonics are spectral components that occur at multiples of the stimulus signal.  It is normal to look at the second, third and fourth harmonic in an ADC.  Somewhere beyond this point, harmonic order becomes less clear because of aliasing and the general term spurious is applied.  In a mathematical sense, the Taylor series coefficients previously discussed predicts these harmonics.

 

Spurious Free Dynamic Range is the range between fullscale and the largest spur, which may or may not be harmonically related.  SFDR is normally determined by sweeping the amplitude of the input signal over a large input rage.  As can be seen in the graph below, SFDR increases and decreases as different codes sets of the ADC are stimulated.  As previously discussed, localized DNL and INL errors are the major contributor to the unsettled nature as the amplitude is swept. 

What are they

As just discussed, the generations of harmonics within data converters can be very complex.  Regardless of the actual complexity, manufacturers usually supply only a hand full of specifications in a data sheet.  These are harmonics, SFDR and IMD (which is also known as two-tone intermodulation).  A good data sheet will include this information not only in a table but in a chart form including both power and frequency sweep formats.

 

 

 

This converter is fairly well behaved in both the amplitude and frequency domain.  As the power level is reduced, the spurious performance (SFDR) remains consistent, changing only a few dB as certain local non-linearities affect performance.  Poorly performing converters would show a rapid improvement in SFDR as the amplitude is reduced signifying that the converter may have problems with slew rate limitations as shown in the graphs below with an ADC preceded by an amplifier.

 

 

Likewise, the frequency sweep plot shows gradual reduction in performance with few significant dips and peaks in performance.  A poorly performing converter will have significantly reduced harmonics before the first Nyquist zone (one half of the sample frequency) is reached.

 

 

Oversampling and Out of Band Placement

As shown in the previous graph, the second and third harmonic are generally the worst spurious that must be dealt with.  Beyond third harmonics, they typically are hidden by the noise of the converter.  As such, it becomes easy to select a sample rate and analog input frequency such that the second and third harmonics fall away from the signals of interest.  Therefore by careful advance planning, an ADC can give much better performance than otherwise possible simply by aligning the signals such that the worst spurious fall “out of band”.  This is further facilitated by the process of over-sampling, which is defined as sampling at a rate much faster than required by Nyquist.  Excess sample rate allows more options in terms of frequency placement as in this example.

 

 

For the case of an encode rate equal to 61.44 MSPS and a signal bandwidth of 5 MHz, placing the analog input somewhere between 7.68 and 15.36 MHz places the second and third harmonics out of band as shown in the table below.  As can be seen, the second and third harmonics fall away from the band of interest and cause no interference to the fundamental components.  It should be noted that the seconds and thirds do overlap with one another and the thirds alias around FS/2.  Although this example is a very simple, it can be tailored to suit many differed applications.

 

Encode Rate:	61.44 MSPS
Fundamental:	7.68 – 15.36 MHz
Second Harmonic:	15.36 – 30.72 MHz
Third Harmonic:	23.04 – 30.72 MHz and 30.72 – 15.36 MHz

 

Strictly speaking, these exact frequencies do not have to be followed.  Many times it may be advantageous for the analog frequencies to be much higher, possibly even at the first IF frequency.  Many available ADCs allow for IF sampling.  The process of sampling at a rate, which is much less than the absolute frequency of interest, is known as under-sampling.  Under-sampling allows the converter to be used similarly to a mixer in the down conversion process.  Although the process of sampling (aliasing) is different than mixing (multiplication), the results are quite similar.  An artifact of under-sampling is that of spectral reversal of certain frequencies.  As in mixers, certain products become reversed in the sampling process such as upper and lower sideband reversal.  The table below shows which cases cause spectral reversal. 

 

Input Signal	Frequency Range	Frequency Shift	Spectral Sense
1st Nyquist Zone	DC - FS/2	Input	Normal
2nd Nyquist Zone	FS/2 - FS	FS-Input	Reversed
3rd Nyquist Zone	FS - 3FS/2	Input - FS	Normal
4th Nyquist Zone	3FS/2 - 2FS	2FS - Input	Reversed
5th Nyquist Zone	2FS - 5FS/2	Input - 2FS	Normal

 

IMD (aka two-tone)

What are they

Intermodulation distortion (IMD) is the distortion cause by the nonlinear aspects of any linear circuit.  This specific distortion results when multiple signals are processed with the nonlinear device, resulting in new spectral terms not present in the original signal.  From the general equation shown below, these terms result when two or more sinusoidal signals are multiplied together.  In this equation, the term associated with k₀ is the circuit offset; k₁ is the normal circuit gain.  However, for k₂ and beyond, these terms result in new spectral terms.  In general, those associated with k₂ result in terms that are the sum and difference of the input frequencies while k₃ terms result in terms found at 2f₁-f₂ and 2f₂-f₁.  Higher order terms are produced as the expansion series is expanded further.

 

 

The effect of intermodulation is shown in the following figure.  Note the terms associated with the second and third order products.

 

 

3^rd Order Intercept Point

Although the terms associated with k₂ are generally associated with a mixer, for some systems they are often unimportant because they fall away from the main signals.  On the other hand, the terms associated with k₃ fall adjacent to the signals of interest.  These terms are responsible for generating what are called the third order intercept products often written as IP3. 

 

A unique characteristic of the 3^rd order terms is that their amplitude increases at a rate three times faster than the signals that generate them.  If the signals generating them could be made sufficiently large, there is a point at which the 3^rd order terms would equal the signals generating them.  This point is known as the third order intercept point.  In general this is a theoretical number because all linear devices have a physical limit on the output level that is reached before the intercept point is determined.  For data converters like ADCs, this corresponds to the clip point.  However, using smaller signals to determine the slope and a reference point, the intercept point can be interpolated by extending the lines of both the input and the third order products to the point they intercept.  This is shown in the graph below. 

 

 

Tolerance of

Although the next section covers tolerance of spurious products in general, intercept point has a special set of tests associated with it.  Linear devices often specify third order intercept performance information.  This can either be input or output referred with the difference being the gain or loss of the device.  Data converters however normally do not provide intercept numbers for two reasons.  First IP3 is normally associated with power measurements.  ADCs are voltage devices and not power devices.  Second, most high quality ADCs have very good intermodulation performance and are often difficult to determine.  However, a similar test called two-tone intermodulation is often provided.  Two-tone intermodulation is the level of distortion that occurs when the converter is stimulated by 2 tones closely spaced as shown in the figure above.  While data converters are not power devices, for a known input termination, the intercept point can be estimated.  This is not a true intercept point, but can be used as long as the input termination conditions do not change.

 

For example an ADC data sheet indicates a two-tone performance of –90 dBc when driven by two signals –7 dBFS.  If the fullscale of the converter is +5 dBm, the two-tone signals are at –2 dBm and the two-tone spurious are at –92 dBm.  Since it is assumed that the ADC will have typical IP3 response, the third order products would increase at a rate of 3 times faster than the input stimulus solving for the point where the two signals would intercept gives the equation:

 

 

Where IP3 is the equivalent intercept point, L_input is the power level of one of the stimulus signals and L_two-tone is the power level of the specified two-tone performance.  Both inputs are in dBm.  Using the numbers as specified above gives an equivalent IP3 of  +43 dBm.  Since data converters do not have gain, this number is valid for both the input and output of the device.

 

IP3 performance for a system can be determined by cascading the performances of each stage.  In determining the cascaded performances, the following equation is often used.  In this equation, it is assumed that each stage contributes is a coherent fashion, thereby giving a worst case number, but is often useful for determining the bounds on system performance.  In this equation, the numbers are all in watts (or milli-watts) and should be reflected either to the input or output as desired using the stage gain information to adjust the numbers appropriately.

 

 

If more than 2 stages are provided, they may all be included in the summation above, remembering that each must be referred to the input or output and expressed in watts to use this equation. 

 

 

To solve this example, both the AFE and ADC must be referred to the input.  This gives input IP3s of +8 dBm and +13 dBm respectively.  Converting these to milli-watts gives, 6.31 mW and 19.95 mW respectively.  Using the equation above gives a cascaded result of +6.81 dBm on the input side or +36.81 dBm on the output side.

 

Selecting the ADC performance needed

No matter the source of spurious products, either harmonics or IMD products, every system has a certain tolerance of those spurious.  Many times, the degree of tolerance is based on some specification.  Once this has been determined, the next step is to determine the overall performance of the system and the contribution from the ADC.  Like strictly linear devices, the spurious generated by the ADCs contribute to the overall spurious performance of the system.  In a typical system, it is frequently assumed that the spurious generated by each component are not correlated with one another although they are at the same frequency.

 

 

If the overall performance requirement is known and referred to the input, the required ADC performance can be determined.  In the diagram above, the analog front end has been specified such that the spurious content of interest is referred to the output.  This may be because the device was specified in this manner or it may be from bench measurements where the output performance was directly observed using a spectrum analyzer.  Also the gain of that stage is known.  Given the required input referred performance and the knowledge of how the analog section performs, the required performance from the ADC can be calculated. 

 

The first step would be to convert the analog front-end (AFE) performance to input referred performance.  At the output, it has been determined that it would provide –70 dBm of spurious contribution for the specified input condition.  Since it also has 20 dB of gain, when referred to the input, this is a level of –90 dBm assuming that constant impedance exists throughout the system, which is assumed to be 50 ohms.

 

Converting both the requirement and the input referred AFE to power using the equation:

 

 

Using –80 dBm and –90 dBm gives powers of  and  watts respectively.  Since these are rms power, the total rms power is simply the sum of all of the contributing sources, in this example, the sum of the AFE distortion plus the ADC distortion.  Since we know the total and the AFE but not the ADC, the equation would be written:

 

 

Substituting the numbers above gives  watts that the ADC can contribute to the total spurious power.  Converting this to dBm on the front end gives –80.46 dBm distortion by the ADC at the input to the system.  To refer to the ADC, the system gain must be applied and gives an ADC performance of –60.46 dBm.  However, most ADCs are specified in reference to their fullscale, not dBm.  In this system, the fullscale has been determined to be +4 dBm and thus, the ADC must provide 64.46 dBFS spurious performance to meet the overall specification of –80 dBm at the input to the system.

 

This analysis is valid for any spurious condition, be it 2^nd or 3^rd harmonic or even spurious generated by two tone testing.  If the system requirements are in respect to rms voltage generated by spurious, they should be converted to power before the procedure outline above can still be used.  The voltages may be converter to power or the rms voltages may be combined using the rms sum of square root of the sum of the squares.

 

An interesting observation is that unlike noise figure, the overall spurious performance is often dominated by the backend of the system.  Thus, the components in the rear of the circuit are often the most critical.  This is generally true because the back end of the circuit has the largest signal levels as they have been gained up with each successive stage, thus requiring generally higher IP3 and spurious performance with each successive gain stage.

Improving the ADC already in your system

Dynamic effects of Static Linearity

As stated earlier in an earlier section, INL and DNL alone are not sufficient to characterize a converters performance for communications applications.  For example, a converter may have a worst case DNL of +2 lsb 1 code from -FS.  Although this is quite a bad error, its effect on a converter in a receiver application will be minimal since the converter rarely uses codes near +/- full-scale except in the case of clipped or near clipped analog input.  Conversely, a converter may have a worst DNL error of +.25, near mid-scale.  After careful examination, it is revealed that there are a series of 4 codes near one another, each of them +.25 lsb.  The net effect on the converter is a localized INL error of +1 lsb, a rather significant error.  As shown in the figure below, a signal that never reaches full scale may never hit the bad codes unless the converter is clipped anyway.  Likewise, a converter with 4 typical errors in the middle of the range will be repetitively exercised causing potential dynamic troubles.  Thus a blanket statement about the INL or DNL of a converter without additional information such as location or repetition is almost useless.

 

 

High-resolution data converters typically use multistage techniques to achieve high bit resolution without large comparator arrays that would be required if traditional ‘flash’ ADC techniques were employed.  The multistage converter typically provides more economical use of silicon.  However, since it is a multistage device, certain portions of the circuit are used repetitively as the analog input sweeps from one end of the converter.  This is shown in the figure below where there is a repetitive nature to the DNL errors.  Although the worst DNL error may be less than .25 lsb, the repetitive nature of the transfer function can play havoc with low-level dynamic signals.  Full scale SFDR may be 88 dBFS, however 20 dB below full-scale, these repetitive DNL errors may cause SFDR to fall to 80 dBFS.

 

The plots below were taken from two different 12-bit ADCs in the same product family.  Although each is quite good, both of the INL and DNL plot pairs clearly show dramatically different linearity characteristics, which is quite common between different die.  What is clear is that both show the signs of the repetitive nature of the repetitive nature of linearity in multi-stage converters.

 

 

Probability

To begin to understand how DNL can effects the dynamic performance of a data converter, it is necessary to examine the probability density function (PDF) of a sinusoidal function stimulating the data converter.  The equation below expresses the probability of any converter code occurring.

 

 

 is the full-scale range of the converter

 is the number of bits in the converter

 the code in question

 is the peak amplitude of the input sinewave

 

By using this equation with a full-scale signal, it is shown that the probability of a full scale code occurring is 1 percent for a 12-bit converter.  In contrast, the probability of a midscale code occurring is only .015 percent, defining the typical ‘cusp’ associated with the PDF of a sinewave.  This is due to the fact that the slew rate of the sine function is greatest at midscale and zero at the max/min.  Therefore, on a per sample basis, the likelihood of sampling the signal at the max/min is greater that at the zero crossing.  In fact, if the PDF array is multiplied by the DNL error array and integrated, the resultant is the total error that could be expected for a full-scale sine wave with the given DNL error.

 

 

What about the case where the input signal is -30 dB below full scale?  In this case, only just over 3 percent of the converter codes are exercised.  In this example, the codes at the peak of the sine wave now have a probability of occurring of 3 percent and midscale codes .5 percent.  As before, if the PDF array for the reduced amplitude sine is multiplied by the DNL errors for those same codes and integrated, then the resultant is the total error that could be expected for the reduced amplitude signal.  If the process is again performed on a signal at -60 dB below full-scale, only .1 percent (4 codes) of the codes are exercise.  For this case the peak codes occur 28 percent of the time and the middle codes 22 percent.  As before, if the PDF array is multiplied by the DNL error array and integrated, the overall error would result.

 

 

 

How does this relate to dynamic performance?  Assume for example that all converter codes exhibit perfect DNL (i.e. 0 error) except for code number 1985, which has a DNL error of +1.5 lsb.  With a full-scale sinusoidal input, the additional error (besides normal quantization error) is 1.5*0.0001555 or 0.00023325 lsbs.  However, with a signal at -30 dB below full-scale, the equation is now 1.5*.03 or .045 lsbs and the contribution is now almost 200 times greater at the reduced signal level than when the input was at full scale .  Furthermore, since the shape of the PDF is a cusp shape as shown in the figure above, it can be expected that dynamic performance can be predicted to gradually worsen as the rim of the cusp approaches code 1985, then quickly return to near perfect performance when the signal falls below -30 dB where code 1985 is no longer exercised.

 

In this example, since the error only occurs only at the signal peak with the reduced signal, the primary contributor as the signal is reduced is the second harmonic.  In a practical converter, the DNL errors are complex and frequently repetitive as shown in the figures of the previous sections.  It is this effect that dither seeks to remove in order to improve (or maintain) as the signal levels are reduced.

 

The Nature of DNL

To understand the nature of DNL in any converter, it is necessary to go into a few more details than earlier in this chapter.  This discussion must look at the architecture of the converter under study.  There is no fixed solution that works for all converters because all have different architectures.  Therefore the solution is specific to the device being used.  However, the general method is the same for most architectures and thus lends itself well by extension.  For this example, the AD9042, a 12 bit, 41 MSPS converter will be examined.  As shown in the figure, this is a multistage converter with a 6-bit ADC followed by a 7-bit converter.  The combined total is 12 data bits plus 1 error correction bit to internally compensate for internal non-linearities.  For any multistage converter to properly operate, a highly accurate digital to analog converter must be employed to convert the first stage ADC (6-bits in the AD9042) back into analog for subtraction from the original input.  In the AD9042, this DAC is nearly 14-bits accurate.  Following the DAC in the architecture is an amplifier that is used to perform the subtraction and gain ranging for the second ADC (7-bits in the AD9042).  Again, the gain of the amplifier must be matched precisely to the range of the second ADC.  If any of these conditions are not exactly met, the result will be mismatches that show up as DNL errors, much worse than those shown in the actual DNL plots.  Not a lot of gain mismatch is required to cause problems.  For example, even if matching is maintained to 12-bits, the DNL error generated could be +/- 1 lsb.  Even if 14-bit matching is achieved, the overall DNL errors will be +/-.25 lsb as in the AD9042.  Thus from the actual DNL plots shown earlier, it is apparent that matching is maintained between 13 and 14 bits despite the fact that the AD9042 is an un-trimmed device.

 

 

Furthermore, in a multistage converter, since the range of the second stage ADC is used over many times, the DNL pattern will repeat many times.  In fact, the DNL repeat count will be 2^N where N is the number of bits in the first ADC.  In the AD9042, N is equal to 6 and the repeat count is therefore 64.  By careful observation of the actual DNL plots above, it is observed that the DNL (or INL) pattern occur 64 times.  This logic is valid for many different multistage converter architectures. 

 

What is Dither & How Can It Help?

Simply put, dither is an uncorrelated signal, usually pseudo random noise, injected into the analog input of the data converter.  Although there are many methods of doing this, two methods are offered.  First, the dither can be generated with a pseudo random digital number generator.  This digital data is put to a DAC that is summed with the input to the ADC under test.  On the digital outputs of the ADC, the digital signal sent to the DAC is subtracted from the converter response.  In this way, the noise summed into the analog input is digitally subtracted from the digital output, causing the SNR performance to appear as normal.  This technique is ideal for large dither signals.  

 

 

The other method is to generate the noise in such a manner that it occurs outside of the band of interest.  Two possible locations for out of band signals are DC and Nyquist.  Typically, one or the other of these two zones are not used in a receiver designs for a variety of reasons.  One of these two locations will typically yield several hundred kilohertz of bandwidth where noise can be placed and later be digitally filtered. 

           

 

The main purpose of dither is to de-localize or randomize the DNL errors of the converter.  In this way, the DNL of all codes appears more uniform and consistent and no longer exhibits the repeated nature seen in the plots above.  To explain how it works, see the expanded portion of the un-dithered DNL plot below. 

 

 

In this segment of a DNL plot, two of the 64 DNL spikes as well the codes between them are seen.  The goal of dither is to make the DNL errors approach a more uniform state so that any given input voltage does not exercise a particularly bad (or good) code, only an ‘average’ of codes both good and bad.

 

The following series of plots show how the differential linearity is ‘averaged’ by convolving the PDF of a Gaussian noise with the DNL plot shown at the first of the series.  In each successive plot, the amount of dither is increased.  The first plot is for a dither of 5.3 codes rms dither, the second 10.6, the third 16 and the last 21.3 codes rms (128 peak to peak) dither.  As the dither is increased beyond this more than one section is averaged and provides little improvement to the overall small signal dynamic performance.  As can be seen, the last two plots of the series have almost identical swings indicating little additional SFDR improvements.

 

 

Optimal dither level for the AD9042 is reached somewhere between 16 and 21.3 codes rms.  This correlates to a dither power of between -35 dBm and -32.5 dBm respectively.  Beyond this, little improvements will be made in small signal dynamic performance.  With these dither powers injected, spurious performance can be generally expected to drop well into the noise floor for non-full scale signals as seen in the dither example below.

 

 

The following plot shows the surface contour for swept dither and swept input amplitude.  This plot yields the effects of dither power on SFDR.  The section on the left rear indicates the dynamic range lost due to the addition of dither power.  This is indicated by a total loss of SFDR due to clipping of the converter.  Operation in this range should be avoided.  However, the balance of the range is a valid operating range.  The axis running from front to back is the input signal power and ranges from about –60 dBFS to 0 dBFS.  Running left to right is dither power corresponding to –54 dBm to about –2.5 dBm. 

 

As can be seen at very low dither powers (-54 dBm), as the analog signal level is increased, the SFDR is good until the level reaches about –30 dBm.  At this point a DNL error is reached and causes poor SFDR (indicated by the purple spike).  If the analog input is increased further, additional purple spikes occur.  To counter this, additional dither power will improve the performance as seen by moving to the left on the graph until the purple spikes no longer appear.